1. Field of the Present Invention
The present invention relates to a germanium semiconductor device and a method of manufacturing the same, and more particularly, to a germanium semiconductor device comprising source and drain regions in a germanium substrate formed by delta-doping, in-situ selective deposition of a silicon-germanium (SiGe) layer containing impurities and diffusion through annealing, and a method of manufacturing the same.
2. Discussion of Related Art
With the trend to various compact, thin and lightweight electrical devices, the scaling-down of a semiconductor device has recently been accelerated. As a CMOS transistor is reduced in size, the device increases in operating speed and integration density. However, when the CMOS transistor is formed to have a gate width of 65 nm or less, it faces many difficulties in process as well as improvement of drive current due to a short channel effect, etc.
To solve these difficulties, methods for modifying a structure of a conventional silicon (Si) MOS transistor and improving electron and hole mobility by applying tensile and compressive strains to a channel are provided. The application of strains to the silicon channel has a difficulty in growing a SiGe layer, that has a larger lattice structure than a Si layer under the channel, while reducing strains without any defect. However, the growth of a SiGe buffer layer requires high technology, which results in poor economical efficiency and reproducibility.
Accordingly, to utilize germanium (Ge) having a 2.5 times faster electron mobility and a 5 times faster hole mobility than those of silicon, recent research on a Ge MOS transistor using a Ge substrate has actively been progressing.
However, the Ge MOS transistor is not easily manufactured because a Ge oxide layer which will be applied to a gate insulating layer and an isolation layer is not stable, and source and drain regions are not easily manufactured by an ion injection method due to low solubility of a Ge single crystal to impurities and fast diffusion rate. In addition, the manufacture of the Ge MOS transistor may result in a decrease in device characteristics because of very high contact resistance between a metal connection and a Ge layer.
Also, much research on a high-k metal oxide layer (a high-k dielectric layer) for application to nano-sized devices has been progressing recently, and some of these devices already have performance suitable for commercialization. Such a high-k dielectric layer can be applied to the Ge MOS transistor as a gate insulating layer, but it still has problems of formation of source and drain regions having a shallow junction depth with high-concentration impurities and high contact resistance between a metal connection and a Ge layer.